Is the order and name of the input/output signals in a DSL model important?
The order of the signals defined in a slot and block definition is not relevant for the model. PowerFactory doesn't assign the signals by order, but it does it using the names. Therefore the name is the relevant information; the name of a signal has to match in the slot and DSL model inside in order to communicate it correctly. DSL is case sensitive then the use of capital and small letters makes a difference.